Semiconductor device and voltage regulator

ABSTRACT

A semiconductor device having a chip size package is disclosed. The chip size package comprises a semiconductor chip having at least a bonding pad, at least a terminal of said chip size package and a reroute trace formed between the bonding pad and the terminal on said chip size package. The reroute trace is formed to have a desired resistance.

TECHNICAL FIELD

The present invention relates to a semiconductor device using a chipsize package (CSP), and more particularly to a semiconductor device inwhich reroute traces are used for providing circuit design withflexibility. The present invention is suitable for a phase compensationcircuit for a voltage regulator placed on the CSP or other analogcircuits placed on the CSP.

BACKGROUND ART

Various kinds of packages for LSI chips are known. Recently, a chip sizepackage (CSP) having almost the same size as the LSI chip, has been putunder development in order to reduce the size of the package.

FIG. 1 shows packaging processes for various kinds of conventional chipsize packages. Reference numeral 101 shown in FIG. 1 shows a packagingprocess for a lead frame package, reference numeral 102 shown in FIG. 1shows a packaging process for a Fine-pitch Ball Grid Array (FBGA) andreference numeral 103 shown in FIG. 1 shows a packaging process for awafer-level CSP.

The packaging process 101 for the Lead frame package and the packagingprocess 102 for the FBGA shown in FIG. 1 are conventional packagingprocesses (a dicing process A1, a die bonding process A2, a wire bondingprocess A3, an encapsulation process A4, a lead forming process A5/alead surface finishing process and a cutting process for singularization(dicing a wafer into single chips) A6 or a terminal finishing processand a cutting process for singularization A7). In these packagingprocesses, each chip processed by a front-end process 104 is cut by thedicing process and the chip is assembled by an assembly process.However, in a packaging process 103 in the wafer level CSP of thepresent invention as shown in FIG. 1, a wafer processed by the front-endprocess is directly processed by the packaging process 103 (a Pi filmforming process A11, a reroute tracing process A12, a post formingprocess A13, an encapsulation process A14, and a terminal grindingprocess A15). Then, the wafer is cut to singularize each chip (a dicingprocess A16).

FIG. 2 shows a sectional view of the chip manufactured by the waferlevel CSP technology. In FIG. 2, reference numeral B1 shows an IC chip(a silicon chip), reference numeral B2 shows an aluminum electrodeplaced on a pad of the IC chip B1, reference numeral B3 shows a barriermetal layer, reference numeral B4 shows a reroute trace layer (Cu)placed on the barrier metal layer B3, reference numeral B5 shows acopper post, reference numeral B6 shows a solder bump (a solder ball),reference numeral B7 shows a passivation layer, reference numeral B8shows a mold layer (for example, a resin encapsulation layer) andreference numeral B9 shows a protection film.

In the conventional wafer level CSP, it is assumed that the aluminumelectrode B2 placed on the pad of the IC chip B1 is connected to thecopper post B5 and the solder bump (the solder ball) B6 only through thereroute trace B4 having a resistance as low as possible.

However, there is a problem that specifications and performance of theCSP are limited by the structure of the IC chip, if it is assumed thatthe aluminum electrode placed on the pad of the IC chip B1 is connectedto the copper post B5 and the solder bump (the solder ball) B6 onlythrough the reroute trace B4 having a resistance as low as possible.

DISCLOSURE OF THE INVENTION

Accordingly, it is a general object of the present invention to providea semiconductor device and a voltage regulator in which theabove-described disadvantage is eliminated.

A more specific object of the present invention is to provide asemiconductor device in which specifications and performance of an ICchip itself can be expanded, and which semiconductor device providescircuit design with flexibility.

Another object of the present invention is to provide a semiconductordevice including a voltage regulator in which oscillation of the voltageregulator can easily be suppressed.

The above objects of the present invention are achieved by asemiconductor device having a chip size package, the chip size packagecomprising:

a semiconductor chip having at least a bonding pad;

at least a terminal of said chip size package; and

a reroute trace formed between said bonding pad and said terminal onsaid chip size package, wherein the reroute trace is formed to have adesired resistance.

The above objects of the present invention are achieved by thesemiconductor device, wherein the chip size package has a plurality ofterminals, each of which is connected to the bonding pad through one ofa plurality of reroute traces.

The above objects of the present invention are achieved by thesemiconductor device, wherein the desired resistance of the reroutetrace is designed by means of lengthening the reroute trace, narrowingthe reroute trace or selecting material of the reroute trace.

According to the present invention, it is possible to provide thesemiconductor device in which the specifications and the performance ofthe IC chip can be expanded, and which semiconductor device providescircuit design with flexibility.

The above objects of the present invention are achieved by thesemiconductor device, wherein the semiconductor chip comprises a voltageregulator circuit, and a load is connected to one terminal connected toone reroute trace having the lowest resistance among the reroute traces,and a phase compensation capacitor is connected to another terminalhaving another reroute trace having a predetermined resistance among thereroute traces.

The above objects of the present invention are achieved by thesemiconductor device, wherein said predetermined resistance is between10 milli-ohms and 10 ohms.

The above objects of the present invention are achieved by thesemiconductor device, wherein the semiconductor chip comprises a voltageregulator circuit, and a load and a phase compensation capacitor areconnected to the terminal of the chip size package connected to saidreroute trace having the desired resistance.

The above objects of the present invention are achieved by thesemiconductor device, wherein the desired resistance of the reroutetrace is designed by means of lengthening the reroute trace, narrowingthe reroute trace of selecting material of the reroute trace.

The above objects of the present invention are achieved by thesemiconductor device, wherein the desired resistance is between 10milli-ohms and 200 milli-ohms.

According to the present invention, it is possible to provide asemiconductor device including a voltage regulator in which oscillationcan easily be suppressed.

As described above, according to the present invention, it is possibleto determine the circuit characteristics of the voltage regulator duringthe CSP manufacturing process so as to use the phase compensationcapacitor. Therefore, the present invention enables providing thecircuit design at the wafer level with flexibility. Further, it is easyto improve the circuit characteristics without changing the circuitdesign at the wafer level. Further, it is possible to provide thevoltage regulator in which a ceramic capacitor is used as a phasecompensation capacitor to prevent the voltage regulator fromoscillating.

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects, features and advantages of the present invention willbecome more apparent from the following detailed description when readin conjunction with the accompanying drawings, in which:

FIG. 1 shows conventional manufacturing processes for various kinds ofchip size packages;

FIG. 2 shows a sectional view of a manufactured chip using a wafer levelchip size packaging technology;

FIG. 3A shows a diagram of the first embodiment of the presentinvention;

FIG. 3B shows a diagram of the first embodiment of the presentinvention;

FIG. 3C shows a diagram of the first embodiment of the presentinvention;

FIG. 3D shows a diagram of the first embodiment of the presentinvention;

FIG. 4A shows a diagram of the second embodiment of the presentinvention;

FIG. 4B shows a diagram of the second embodiment of the presentinvention;

FIG. 5 shows an example of a generic voltage regulator which isoperating;

FIG. 6 shows an internal structure of the generic voltage regulatorshown in FIG. 5;

FIG. 7A shows a graph of frequency response versus gain of an open loopof the voltage regulator that oscillates;

FIG. 7B shows a graph of frequency response versus phase of the openloop of the voltage regulator that oscillates;

FIG. 8A shows a graph of frequency response versus gain of the voltageregulator that does not oscillate;

FIG. 8B shows a graph of frequency response versus phase of the voltageregulator that does not oscillate;

FIG. 9 shows a diagram of the third embodiment (a voltage regulator) ofthe present invention;

FIG. 10 shows a sectional view of a reroute trace pattern of the voltageregulator shown in FIG. 9;

FIG. 11 shows a top view of the reroute trace pattern shown in FIG. 10;

FIG. 12 shows a relationship between the resistance of a resistor Routand a stability factor of the circuit shown in FIG. 9;

FIG. 13 shows a diagram of the fourth embodiment (a voltage regulator)of the present invention;

FIG. 14 shows a sectional view of a reroute trace pattern of the voltageregulator shown in FIG. 13;

FIG. 15 shows a top view of the reroute trace pattern shown in FIG. 14;and

FIG. 16 shows a relationship between the resistance of a resistor Routand a stability factor of the circuit shown in FIG. 13.

BEST MODE FOR CARRYING OUT THE INVENTION

A description will now be given, with reference to the accompanyingdrawings, of embodiments of the present invention.

FIRST EMBODIMENT

FIGS. 3A through 3D show the first embodiment of the present inventionin which a bonding pad of an IC chip is connected to a plurality ofsolder bumps that are output terminals of a chip size package (CSP),through a plurality of reroute traces.

FIG. 3A shows a configuration in which a bonding pad 1 of the IC chip isconnected to two solder bumps 2 and 3 through two reroute traces 4 a and4 b. FIG. 3B shows an equivalent circuit of the configuration shown inFIG. 3A. FIG. 3C shows a configuration in which a bonding pad 11 of theIC chip is connected to three solder bumps 12, 13 and 14 through threereroute traces 15 a, 15 b and 15 c. FIG. 3D shows an equivalent circuitof the configuration shown in FIG. 3C. It is understood that a bondingpad of the IC chip can be connected to more than three solder bumpsthrough the reroute traces.

This configuration enables connecting each bonding pad to a plurality ofsolder bumps placed on desired positions on the chip size packagethrough the reroute traces. Therefore, it is possible to output a signalsupplied from the bonding pad of the IC chip through the solder bumpsplaced on desired positions on the chip size package. As a result, theapplication area of the chip size package can be largely expanded.

SECOND EMBODIMENT

Next, a second embodiment of the present invention will be explained.

In the first embodiment of the present invention, the resistance of areroute trace is not taken into account (or it is assumed that thereroute trace has a resistance of nearly zero). In the second embodimentof the present invention, the resistance of a reroute trace thatconnects a bonding pad with one of plurality of solder bumps is designedto have a predetermined value.

FIGS. 4A and 4B show the second embodiment of the present invention.FIG. 4A shows an equivalent circuit of the configuration shown in FIG.3A in which the resistance of the reroute trace 4 a is designed to benearly zero and the resistance of the reroute trace 4 b is designed tobe a value of r1. FIG. 4B shows an equivalent circuit of theconfiguration shown in FIG. 3C in which the resistance of the reroutetrace 15 a is designed to be nearly zero, the resistance of the reroutetrace 15 b is designed to be a value of r2, and the resistance of thereroute trace 15 c is designed to be a value of r3. Selection of theresistance of each reroute trace is design a matter and the value ofeach resistance depends on the circuit to which the present invention isapplied. Employing this configuration, the application area of the chipsize package can be further expanded compared to the first embodiment ofthe present invention mentioned above.

THIRD EMBODIMENT

Next, the third embodiment of the present invention will be explained.In the third embodiment, the present invention is applied to a voltageregulator. However, it is understood that the present invention can beapplied to any analog circuit and various kinds of semiconductordevices. FIG. 5 show an example of a circuit diagram of a voltageregulator which is operating. In FIG. 5, a capacitor 21 having acapacitance of Cout is connected between an output terminal Vout of thevoltage regulator 20 and a ground GND, and a capacitor 22 having acapacitance Cin is connected between an input terminal Vin of thevoltage regulator 20 and the ground GND in order to stabilize an inputvoltage and an output voltage. A resistance ESR (Equivalent SeriesResistance) shows the internal resistance of the capacitor 21.

FIG. 6 shows an internal structure of the example of the generic voltageregulator. As shown in FIG. 6, the generic voltage regulator 30 has aconstant voltage source 31, a differential amplifier 32, an outputtransistor 33 and resistors 34 and 35. The generic voltage regulator 30may oscillate because the resistors 34 and 35 construct a feed backcircuit. VDD shows an input terminal of power, Vout shows an outputterminal of the voltage regulator and GN shows ground.

FIG. 7A shows frequency response versus gain of an open loop of thegeneric voltage regulator 30 and FIG. 7B shows frequency response versusphase of the open loop of the generic voltage regulator 30.

The generic voltage regulator 30 usually has two or three poles in thedifferential amplifier 32 (having two stages) and the output transistor33. When one pole exists, the open loop gain of the generic voltageregulator 30 is reduced 6 dB/octave and the phase of the open loop isdelayed 90 degrees. Therefore, the frequency response of the open loophas the gain characteristics shown in FIG. 7A and the phase delaycharacteristics shown in FIG. 7B. Because there is a frequency at whichthe phase delay is 180 degrees, the generic voltage regulator 30 mayoscillate when the control loop is closed to construct a feed back loop.Therefore, compensating is needed the phase in order to prevent thegeneric voltage regulator 30 from oscillating.

The phase compensation is performed inside of the voltage regulator 20.However, the phase compensation uses zero, which is an inverse of apole, which is formed by both the capacitance Cout and the resistanceESR of the capacitor 21 connected to the output terminal Vout. In FIG.8B, the zero is placed at a frequency of 1/·(2*π*Cout*ESR) [Hz].Therefore, it is possible to advance the phase of the open loop in ordernot to delay the phase at a frequency point C more than 180 degree. As aresult, it is possible to prevent the voltage regulator 20 fromoscillating.

There are several kinds of capacitors 21, such as a tantalum capacitorand a ceramic capacitor, used for the voltage regulator 20. The ESR ofthe tantalum capacitor is several ohms and the ESR of ceramic capacitoris several tens of milli-ohms.

When the tantalum capacitor having a capacitance of several microFarads, which is commonly used, is used for the phase compensation, thezero emerges at a frequency at which the open loop gain is about 0 dB.The phase margin is reduced to around zero degrees at the frequency atwhich the open loop gain is about 0 dB because the phase is delayedalong with the increase of the frequency. Therefore, the phase is easilycompensated for by the tantalum capacitor having a capacitance ofseveral micro Farad.

However, for the ceramic capacitor, the zero emerges at a higherfrequency than that of the tantalum capacitor, because the ESR of theceramic capacitor having the same capacitance as the tantalum capacitoris less than the ESR of the tantalum capacitor. As a result, the phasecompensation value is decreased and the phase cannot be compensated forsufficiently. Therefore, it is required to add a resistance to the ESRof the ceramic capacitor by some means. If the ESR is increased byserially connecting a resistor to the ESR, the phase can be compensatedfor easily.

This requirement is achieved by placing the voltage regulator on the CSPof the present invention. It is then possible to serially connect aresistor, constructed by means of the reroute trace, to the ESR, byusing the CSP of the present invention. As a result, the phasecompensation for the voltage regulator can be easily performed.

Next, the third embodiment of the present invention in which a voltageregulator is placed on the CSP will be explained. As shown in FIG. 2, inthe CSP, a protection film B9 is deposited on the passivation layer B7of the IC chip B1 and the reroute trace B4 is deposited on the aluminumelectrode B2 and connected to the copper post B5. Then, the resinencapsulation layer B8 is deposited and finally, the solder bump (thesolder ball) B6 is placed on the copper post B5.

As described above, serially connecting a resistor to the ESR tofacilitate the phase compensation is needed. To serially connect aresistor to the ESR, a resistor is serially connected at the output ofthe voltage regulator 20.

There are two ways to serially connect a resistor at the output of thevoltage regulator 20. One way is shown in FIG. 9. In FIG. 9, the bondingpad of the output of the IC is connected to two solder bumps through tworeroute traces by means of the present invention as shown in FIG. 4A.This construction can completely prevent a voltage drop at the input ofthe load, caused by a load current.

As shown in FIG. 9, the bonding pad 41 of the output of the voltageregulator 40 is connected to solder bumps 42 and 43. A load 47 isconnected to the solder bump 42 and the capacitor 45 having acapacitance of Cout and a resistance 46 of Resr is connected to thesolder bump 43. A reroute trace between the bonding pad 41 and thesolder bump 42 is designed to have a resistance of nearly zero. On theother hand, a reroute trace between the bonding pad 41 and the solderbump 43 is designed to form a resistor 44 having a resistance of Rout(several hundred milli-ohms) to serially connect the resistor 44 to theResr 46. This can be achieved by deliberately lengthening or narrowingthe pattern of the copper reroute trace between the bonding pad 41 andthe solder bump 43. The construction shown in this embodiment cancompletely prevent a voltage drop at the input of the load 47, caused bya load current. Therefore, it is possible to serially connect theresistor 44 to the Resr 46 without a voltage drop at the input of theload 47. As a result, it is easy to compensate for the phase of the openloop.

Further, even if the number of terminals are increased, the area size ofthe CSP remains unchanged because of the CSP. It is also possible toform a plurality of reroute traces and terminals, each of which reroutetrace has a different resistance, to be selected for the capacitor to beused, in order to serially connect the resistor to the Resr of thecapacitor to optimally match the capacitor to be used. FIG. 10 shows asectional view, including the reroute trace pattern, of the voltageregulator shown in FIG. 9 and FIG. 11 shows a top view of the reroutetrace pattern shown in FIG. 10.

In FIG. 9, the resistance Rout of the resistor 44 is as follows.

The capacitor 45 commonly used has a capacitance of 0.1 to 10 microFarads. In the embodiment shown in FIG. 9, the resistance Rout of theresistor 44 can have a large value because the load 47 is connected tothe solder bump 42 that is connected to the bonding pad 41 through thereroute trace having the resistance of nearly zero. In FIG. 9, it issuitable for the resistor 44 to have the resistance Rout of between 10milli-ohms and 10 ohms. FIG. 12 shows a relationship between theresistance Rout of the resistor 44 and a stability factor of the circuitshown in FIG. 9. A mark “X” shows that the circuit oscillates. A mark“O” shows that the circuit does not oscillate. When the resistance Routof more than 10 ohms is used, it is still possible to prevent thecircuit from oscillating. However, it is difficult to form a resistor 44having such a high resistance using the reroute trace because of thelarge reroute trace area. Therefore, in this embodiment, it is suitablefor the resistor 44 to have the resistance Rout of between 10 milli-ohmsand 10 ohms.

In the embodiment, the voltage regulator is placed on the CSP and thephase compensation is performed on the CSP to prevent the voltageregulator from oscillating. However, it is understood that the presentinvention can be applied to the various kinds of analog circuits.

This can be achieved by deliberately lengthening or narrowing or bothlengthening and narrowing the pattern of the copper reroute tracebetween the bonding pad 41 and the solder bump 43, or this can also beachieved by changing the material to a barrier metal, such as chromium(Cr) or titanium (Ti). As a result, the resistance Rout can be designedto any desired value.

As described above, according to the embodiment, it is possible todetermine the circuit characteristics during the CSP manufacturingprocess. Therefore, the present invention enables providing the circuitdesign at the wafer level with flexibility. Further, it is easy toimprove the circuit characteristics without changing the circuit designat the wafer level.

Further, it is possible to increase the number of terminals of the CSPwithout increasing the area size of the CSP. Therefore, it is possibleto form a plurality of terminals, each of which is for a different use.As a result, this construction can completely prevent the voltage dropat the input of the load, caused by the load current. Further, it ispossible to select a capacitor for the phase compensation among variouskinds of capacitors because it is possible to form a plurality ofterminals connected to different resistors.

FOURTH EMBODIMENT

Another way is shown in FIG. 13. FIG. 13 shows a diagram of the fourthembodiment (a voltage regulator) of the present invention. As shown inFIG. 13, the bonding pad 41 of the output of the IC chip 40 is connectedto a solder bump 42 through a reroute trace 44 by means of the presentinvention. A load 47 and a capacitor 45 are connected in parallel to thesolder bump 42. The reroute trace 44 has a resistance of Rout. Theresistance Rout is designed to have a desired value according to thepresent invention. This can be achieved by deliberately lengthening ornarrowing or both lengthening and narrowing the pattern of the copperreroute trace 44 between the bonding pad 41 and the solder bump 42, orthis can also be achieved by changing the material to a barrier metal,such as chromium (Cr) or titanium (Ti). As a result, the resistance Routis connected in series to the Resr to optimally match the capacitor tobe used. FIG. 14 shows a sectional view, including a reroute tracepattern, of the voltage regulator shown in FIG. 13 and FIG. 15 shows atop view of the reroute trace pattern shown in FIG. 14.

In FIG. 13, the resistance Rout of the resistor 44 is as follows.

The capacitor commonly used has a capacitance of 0.1 to 10 micro Farads.However, the resistance Rout of reroute trace 44 is connected betweenthe bonding pad 41 of the IC chip 40 and the solder bump 42 and the load47 is also connected to the solder bump 42, so that Rout and the load 47are serially connected. As a result, a drive ability of the voltageregulator becomes low. In FIG. 13, it is therefore suitable for theresistor 44 between the bonding pad 41 and the solder bump 42 to havethe resistance Rout of between 10 milli-ohms and 200 milli-ohms.

FIG. 16 shows relationships between the resistance of a resistor Routand a stability factor and other characteristics of the circuit shown inFIG. 13. A mark “X” shows that the circuit oscillates. A mark “O” showsthat the circuit does not oscillate. A mark “S” shows a state which iseven more stable than the state shown in the mark “O”. FIG. 16 showsthat the it is suitable for the resistor 44 between the bonding pad 41and the solder bump 42 to have the resistance Rout of between 10milli-ohms and 200 milli-ohms. “Other characteristics” in FIG. 16 meansa voltage drop that is caused by a load current through the resistanceRout. The higher the resistance Rout becomes, the more the voltagedrops.

As described above, according to the embodiment, it is possible todetermine the circuit characteristics of the voltage regulator duringthe CSP manufacturing process. Therefore, the present invention enablesproviding the circuit design at the wafer level with flexibility.Further, it is easy to improve the circuit characteristics withoutchanging the circuit design at the wafer level.

As described above, according to the embodiment, it is possible toprevent the voltage regulator from oscillating by using the phasecompensation capacitor connected to the terminal of the CSP connected tothe reroute trace having a resistance between 10 milli-ohms and 200milli-ohms.

According to the present invention, it is possible to provide asemiconductor device in which specifications and performance of an ICchip can be expanded, and which semiconductor device provides circuitdesign with flexibility.

Further, according to the present invention, it is possible to provide asemiconductor device including a voltage regulator in which oscillationcan easily be suppressed.

Because the circuit constants (for example, a resistance of the reroutetrace) determined during the manufacturing process of the CSP are usedfor the phase compensation, it is possible to improve thecharacteristics of the voltage regulator without changing the circuitdesign at the wafer level by means of changing the design of the reroutetrace on the CSP. Therefore, the margin for the circuit design at thewafer level is improved. Especially, because of this design margin, itis possible to easily develop the voltage regulator in which a ceramiccapacitor is used as the phase compensation capacitor.

The present invention is not limited to the specifically disclosedembodiments, but variations and modifications may be made withoutdeparting from the scope of the present invention.

The present application is based on Japanese priority application No.2001-272091 filed on Sep. 7, 2001 and Japanese priority application No.2001-272098 filed on Sep. 7, 2001, the entire contents of which arehereby incorporated by reference.

1. A semiconductor device having a chip size package, said chip sizepackage comprising: a semiconductor chip having at least a bonding pad;at least a terminal of said chip size package; and a reroute traceformed between said bonding pad and said terminal on said chip sizepackage, wherein said reroute trace is formed to have a desiredresistance, wherein said chip size package has a plurality of theterminals, each of which is connected to said bonding pad through one ofa plurality of said reroute traces, and wherein said semiconductor chipcomprises a voltage regulator circuit, and a load is connected to oneterminal connected to one reroute trace having a lowest resistance amongsaid reroute traces, and a phase compensation capacitor is connected toanother terminal connected to another reroute trace having apredetermined resistance among said reroute traces.
 2. The semiconductordevice as claimed in claim 1, wherein said predetermined resistance isbetween 10 milli-ohms and 10 ohms.
 3. A semiconductor device having achip size package, said chip size package comprising: a semiconductorchip having at least a bonding pad; at least a terminal of said chipsize package; and a reroute trace formed between said bonding pad andsaid terminal on said chip size package, wherein said reroute trace isformed to have a desired resistance, wherein said semiconductor chipcomprises a voltage regulator circuit, and a load and a phasecompensation capacitor are connected to said terminal of said chip sizepackage connected to said reroute trace having said desired resistance.4. The semiconductor device as claimed in claim 3, wherein said desiredresistance of said reroute trace is designed by means of lengtheningsaid reroute trace, narrowing said reroute trace or selecting a materialof said reroute trace.
 5. The semiconductor device as claimed in claim3, wherein said desired resistance is between 10 milli-ohms and 200milli-ohms.